Due to rapid pace of CMOS technological developments, the size of transistors has reduced leading to lower costs and increased performance. The gate oxide thickness has become thinner, reducing the operating voltages for lower power consumption. Simultaneously, the maximum voltages of the terminals (source, drain and gate) of the transistor need to be designed correspondingly lower to ensure the lifetime of the devices. However, concerning the compatibility of CMOS integrated circuit interface protocols in a micro-electronic system, the chips manufactured with advanced CMOS processes have a signal interface voltage level that is higher than their standard voltage. Such high voltages at the thin gate oxide may damage the gate oxide. Therefore, the input/output circuit (I/O) must be carefully designed to resolve this problem. A prior art hybrid voltage I/O buffer having a thin oxide device can transmit output signals between 0V to VDD and receive input signals between 0V to 2×VDD; or can transmit output signals between 0V to 2×VDD but have no receiving capabilities.
Please refer to FIG. 1. FIG. 1 is a block drawing of a prior art hybrid voltage output buffer. A prior art hybrid voltage output buffer 10 has a three-mode control circuit 11, a level converter 12, a first buffer 13, a second buffer 14 and an output stage circuit 15. The output stage circuit 15 has two stacked PMOS transistors (P1 and P2) and NMOS transistors (N1 and N2). The transistors P1 and P2 are 2.5V devices, while transistor N1 is a 1V device, and transistor N2 is a 2.5V NMOS transistor with a threshold voltage of −0.1 V. Because the gate voltage of the transistors P2 and N2 are biased by 1V (VDD), the gate-source voltage and gate-drain voltage of the transistors P2 and N2 are not higher than 2.5V. To prevent the gate oxide of transistor P1 from overstress and to completely turn off transistor P1, voltage range at point PU should be between 1V to 3.3V. The NMOS transistor N2 can increase the driving capabilities of the output buffer, but it also causes serious subthreshold leakage currents. If the voltage at the output node (OUT) is 3.3V, due to the serious subthreshold leakage current at the transistor N2, the voltage at node Y may exceed 1V. Therefore, a transistor P3 is used to keep the maximum voltage at node Y to 1V. Moreover, the prior art hybrid voltage output buffer can only transmit output signals between 0V to 2×VDD but has no receiving function.
Please refer to FIG. 2. FIG. 2 is a circuit diagram of a prior art level converter of a hybrid voltage output buffer. The prior art level converter 12 is used for converting 0/1V voltage amplitudes to 1/3.3V voltage amplitudes. When the IN signal input node is 1V and the INB signal input node is 0V, the voltage at node B1 is pulled down to 0V, and the transistor P5A is on. After the transistor P5A is on, the voltage of the OUTB output node is 1V, and the transistors P4B, P1B are on. Therefore, the voltages of the OUT output node and the B2 node are 3.3V. Because PMOS transistors pull down the voltages of the node OUT and OUTB too slowly, two coupled NMOS transistors N3A and N3B are used for increasing pull-down speed. In addition, in the prior art level converter 12, the voltage levels of the nodes C1 and C2 are uncertain.
Therefore, it is desirable to provide an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices to mitigate and/or obviate the aforementioned problems.